Saturday, April 28, 2012

High-Level Synthesis without IP Hassels?

Start-up Algotochip offers illusive C-to-chip generation in record time, but raises questions of automation vs. customization and IP ownership.
Start-up Algotochip emerged from stealth mode this week at the Globalpress Electronics Summit 2012 in Santa Cruz, CA. The company announced delivery of their silicon solution based on MimoOn’s LTE reference chain, a wireless industry platform for Software Defined Radio (SDR)
Algotochip – short for Algorithm to chip – claims to create production-ready System-on-Chip (SoC) designs from C-code algorithms. Creating low-level, hardware RTL-code from high-level, software C-code is a long sought goal of the electronic design automation (EDA) industry. What makes Algotochip’s position unique is the claim to deliver silicon hardware in as little as 8 to 16 weeks – instead of the more typical months or years. How is this possible?
Satish Padmanabhan, CTO, claims the secret to the companies fast turnaround time lies in the hardware-software partitioning process.
“Designers can not define a complete system in C or System-C since there is no cycle-based information in C-code,” explained Padmanabhan. “One must take the C-code and then decide what needs to run in programmable (software) and non-programmable (hardware) implementations.”
Typical chip designs start with some amount of existing RTL code. But to do high-level synthesize, engineers must start at the architectural levels using C algorithmic code. At this higher level of abstraction, functions have not yet been apportioned to hardware and software implementations. This is where Algotochip claims to help, by solving the difficult challenges of hardware and software tradeoff decisions.
According to the company, customers need only submit their system specification, C-code with test vectors. The company will use these inputs to partition a solution in hardware (SoC, S-ASIC or FPGA) and software (compiler, simulator) and firmware.
How does this approach compare to other design service businesses like eSilicon and Open Silicon? According to the Algotochip’s Padmanabhan, time is the big differentiator as measured in weeks (8 to 16 weeks typically) rather than months or years to tape out.
In terms of semiconductor intellectual property (IP), Algotochip will incorporate third-party IP or will create customer specific IP from proprietary C-code algorithms. Interestingly, the company claims that their customers will retain all intellectual property rights pertaining to the finished design. Some critics doubt this claim as IP makes up a significant portion of revenue for most chip design service companies.
Another area of concern is whether Algotochip SoCs will really be as power-efficient as those that use traditionally longer-time frame development tools and processes. The short development process – 8 to 16 weeks – suggests to some that the Algotochip offers a more customized rather than completely automated approach for C-to-RTL silicon creation.
Time will tell if Algotochip’s design services can really beat traditional C-to-Chip methods for timely and power-sensitive SoC development. Related issues such as IP ownership should also become clearer after the company enjoys further customer engagements.

Originally published on "IP Insider"

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